1. Field of the Invention
The present invention relates to a synchronous semiconductor memory, and more specifically to a synchronous dynamic random access memory having a reduced number of registers.
2. Description of Related Art
At present, an increase of an operation speed of microprocessors is remarkable, and an operation frequency reaches more than 100 MHz. Development for obtaining a memory which can operate under the operation frequency of the microprocessor, is actively being conducted.
Among memories operating at a high speed, a synchronous dynamic random access memory (abbreviated to a "synchronous DRAM") is particularly sought from a market with the strongest demand. In brief, the synchronous DRAM has a clock input terminal for receiving an external clock, and is configured to latch a command such as a reading command and a writing command in synchronism with a rising of the clock pulse supplied to the clock input terminal, and to output a read-out data or to receive data to be written.
Referring to FIG. 1, there is shown a block diagram of illustrating a whole construction of the conventional synchronous DRAM, which is constructed in accordance with a so called "output latching method".
The shown synchronous DRAM comprises a command buffer 101 receiving a plurality of command signals 22-1 to 22-m, a clock buffer 103 receiving an external clock signal 23, and an address buffer 104 receiving a plurality of address signals 21-1 to 21-n. The clock buffer 103 generates an internal reference clock 25 in synchronism with the external clock signal 23.
The internal reference clock 25 is supplied to the command buffer 101, the address buffer 104, and a burst control circuit 105. At a so called "high edge" timing of the internal reference clock 25 where the internal reference clock 25 changes from a low level to a high level, the command buffer 102 latches and outputs a plurality of internal command signals 26-1 to 26-m corresponding to the command signals 22-1 to 22-m, and the address buffer 104 latches and outputs a plurality of internal address signals 24-1 to 24-n corresponding to the address signals 21-1 to 22-n. Therefore, it can be deemed that, at the timing the clock signal 23 changes from a low level to a high level, the command signals 22-1 to 22-m and the address signals 21-1 to 21-n are fetched into the command buffer 101 and the address buffer 104, respectively.
A command decoder 102 receives and decodes the internal command signals 26-1 to 26-m, to output various internal commands including a read command 27, a write command 227, an activation command 228, a precharge command 229, etc. which cause to start various functions including a reading, a writing, an activation, a precharging, etc. In the following, only parts relating to only the reading operation will be described.
The read command 27 is supplied to the burst control circuit 105, which generates various control signals in response to the read command 27 and in synchronism with the internal reference clock 25.
Here, the "burst" or "burst mode" is one of various features characterizing the synchronous DRAM. In a conventional dynamic random access memory (DRAM), in response to a reading address supplied from an external, data stored at the reading address is read out, so that one data is outputted in response to one address inputting. In the synchronous DRAM, on the other hand, when one address is supplied from an external, a series of internal addresses starting from the address supplied from the external, are sequentially and regularly generated in the inside of the synchronous DRAM chip, in synchronism to a series of clock signals such as the external clocks 23, so that data items stored at the internally generated addresses are continuously read out in synchronism with the clock signal.
The above mentioned operation of reading out a plurality of continuous data items in synchronism with the clock signal, is called a "burst" operation, and the length of the data train which can be read out and outputted by designating one address, is called a "burst length". In general, the burst length includes 2, 4 and 8, in which, for each one read command, data of two bits, or four bits, or eight bits are read out and outputted through each one input/output pin in synchronism with the clock signal, respectively.
Returning to FIG. 1, the burst control circuit 105 has the purpose of repeating the reading operation by the bit number of the burst length. For this purpose, the burst control circuit 105 drives a column decoder 107, a data amplifier 110 and an input gate control circuit 111 by activation signals 235, 236 and 210, respectively, which are generated in synchronism with the internal reference clock 25.
Selection and reading-out of data from a memory cell array 106 are similar to those performed in the conventional DRAM. In brief, a row decoder 108 associated to the memory cell array 106, decodes a row address composed of row address signals 29-1 to 29-q and selects a word line before the reading operation starts. Data of memory cells connected to all gates connected to the selected word line are supplied to a sense amplifier block 109 associated to the memory cell array 106, and are retained in the sense amplifier block 109.
One sense amplifier is selected from the sense amplifier block 109 by the column decoder 107 associated to the memory cell array 106 and receiving and decoding a column address composed of the column address signals 24-1 to 24-n. Thus, the read-out data is supplied from the selected sense amplifier through a pair of read-out lines 211 and 212 to the data amplifier 110.
A construction and operation succeeding to the above mentioned construction and operation are a characterized portion of the synchronous DRAM. The data amplifier 110 further amplifies the data on the read-out lines 211 and 212, and transfers the amplified data through a pair of read/write bus lines 213 and 214 to a first input gate 113 and a second input gate 115.
Here, in response to the activation signal 210 outputted from the burst control circuit 105 at substantially the same timing as the activation signals 235 and 236, the input gate control circuit 111 is brought into a standby condition. In this standby condition, the input gate control circuit 111 outputs a first input gate switch signal 222 in response to a data output signal 215 which is transferred from the data amplifier 110 at substantially the same timing as the data signals are transferred through the read/write bus lines 213 and 214 to the first input gate 113 and the second input gate 115, respectively. This first input gate switch signal 222 is supplied to the first input gate 113, and is in the form of a one-shot pulse, so that, only during a period in which the first input gate switch signal 222 in the form of the one-shot pulse is active, the first input gate 113 is opened, namely, rendered conductive. As a result, the first item of data in the burst transferred through the read/write bus lines 213 and 214 is latched in a first register 240, and is held in output lines 216 and 217 of the first input gate 113.
After the above mentioned operation, in response to a next clock signal 23, a second item of data in the burst is transferred to the read/write bus lines 213 and 214, and it then latched in a second register 241, similarly to the above mentioned operation.
Here, a "latency" characterized in the reading operation of the synchronous DRAM will be described. Assuming that a cycle (or period) of the clock signal 23 is called a "clock cycle", if a time length starting from a "high edge" of the clock signal 23 where the read command is fetched and terminating when the first data is latched in the first register 240, is substantially equal to the clock cycle, it is said that the synchronous DRAM is used as being a synchronous DRAM of the latency 2.
In the latency 3, two times the clock cycle is required until the first data is latched in the first register 240. In the latency 4, three times the clock cycle is required until the first data is latched in the first register 240. From these relations it would be seen that the smaller (or shorter) the clock cycle is, the larger the latency becomes.
In the case of the latency 2, assuming that the clock signal 23 for fetching the read command is a first clock and the clock signal supplied next to the clock signal 23 for fetching the read command is a second clock, the read-out data is outputted in response to the second clock. This means that a time of one cycle is required until the data is latched and it has become ready to output the data.
The latency control of this latency 2 will be described with reference to FIG. 1, again.
A latency control circuit 117 receives the internal reference clock 25 and the read command 27, and generates an output enable signal 224 in synchronism with the high edge of the second internal reference clock 25.
In response to the output enable signal 224 and in synchronism with the internal reference clock 25, an output gate control circuit 112 generates a first output gate switch signal 223 in the form of a one-shot pulse, to a first output gate 114. During an active period of the first output gate switch signal 223 in the form of the one-shot pulse, the data latched in the first register 240 is transferred to a pair of read bus lines 218 and 219, and latched on the read bus lines 218 and 219 at the termination of the one-shot pulse of the first output gate switch signal 223. The latched data is outputted through an output buffer 118 to an external input/output pin 230.
Similarly, the data latched in the second register 241 is transferred through a second output gate 116 which is opened or rendered conductive by a second output gate switch signal 234 in the form of a one-shot pulse generated in synchronism with the internal reference clock 25, alternately with the first output gate switch signal 223. Thus, the data latched in the second register 241 is outputted through the output buffer 118 to the external input/output pin 230.
Referring to FIG. 2, there is shown a timing chart illustrating how the data of the two registers 240 and 241 is alternately transferred and outputted. In FIG. 2, Reference Numerals given to various signal waveforms correspond to nodes given with the same Reference Numerals in FIG. 1, and although the explanation of the operation has been already made, the explanation will be made again but now with reference to FIG. 2.
Namely, in synchronism with a rising of the one-shot pulse of the first gate switch signal 222 from the input gate control circuit 111, the "DATA 1" is transferred through the first input gate 113 to the output lines 216 and 217 of the first input gate 113. At a falling edge of the one-shot pulse of the first output gate switch signal 223 from the output gate control circuit 112, the "DATA 1" on the output lines 216 and 217 of the first input gate 113 is transferred through the first output gate 114 to the read bus lines 218 and 219. On the other hand, in synchronism with a rising of the one-shot pulse of the second input gate switch signal 233 from the input gate control circuit 111, the "DATA 2" is transferred through the second input gate 115 to the output lines 231 and 232 of the first input gate 115. At a falling edge of the one-shot pulse of the second output gate switch signal 234 from the output gate control circuit 112, the "DATA 2" on the output lines 231 and 232 of the second input gate 115 is transferred through the second output gate 116 to the read bus lines 218 and 219. Thereafter, "DATA 3" and succeeding data are outputted in a similar manner until the output data reaches the burst length.
Now, why the first and second registers 240 and 241 are required in synchronous DRAM shown in FIG. 1, namely, why two registers are required in the case of the latency 2 in the conventional synchronous DRAM, will be explained with reference to FIG. 3.
In FIG. 3, considering a flow of an internal data transfer within the synchronous DRAM, when the internal data transfer flow is divided into two stages, namely, a former stage and a later stage, by using as a boundary an input gate of the registers 240 and 241, the former stage is called a "stage 1". In addition, a "stage 2-1" means the first register 240, and a "stage 2-2" means the second register 241. A "stage 3" correspond to the read bus lines pair 218 and 219.
Now, a "first data transfer time" is a time from the moment the reading operation starts in response to the internal reference clock 25 to the moment the read-out data reaches to the register. This first data transfer time is independent of the clock cycle, namely, is asynchronous to the clock. A "second data transfer time" requires the same time as the "first data transfer time".
In the "stage 2-1", there is a "first data waiting time" which corresponding to the "first data transfer time" and in which no operation occurs. Furthermore, a latching time (from a timing 4-2 to a timing 4-3) is required in which the data is supplied to the first register 240 and latched in the first register 240. Succeedingly, an outputting time (from the timing 4-3 to a timing 4-4) is required in which the data is outputted to the "stage 3". At this time, just before, or around, or just after a starting (timing 4-3) of the outputting time of the "stage 2-1", the "stage 1" receives the internal reference clock 25 so that the "second data transfer time" starts.
As mentioned above, since the "second data transfer time" has a constant time length, a time 4-6 where the latching starts in the stage 2-2, is determined by a constant time length from the high edge of the internal reference clock 25. However, the first data outputting time starting from the time 4-3 and terminating at the time 4-4, is dependent upon the clock cycle. Therefore, it is so designed that the data is outputted at an intermediate timing between (respective high edges of) second and third clock signals 23.
Therefore, the outputting time of the stage 2-1 and the input time of the stage 3 are shifted forward in time if the clock cycle is short, and shifted backward in time if the clock cycle is long.
As seen from the above, if the clock cycle becomes long and exceeds a certain value, the outputting time in the stage 2-1 and the second data latching time in the stage 2-2 overlap in time. Therefore, if only one register was prepared, data collision occurs.
In order to prevent this data collision, two registers are provided as shown in FIG. 1.
Referring to FIG. 4, there is shown a circuit diagram of the two registers 240 and 241 incorporated in the synchronous DRAM shown in FIG. 1.
In the circuit shown in FIG. 4, first and second registers 830 and 831 correspond to the registers 240 and 241 incorporated in the synchronous DRAM shown in FIG. 1, respectively. Therefore, a circuit scale of the registers shown in FIG. 4 could be imagined.
In the circuit shown in FIG. 4, furthermore, lines 85 and 86 correspond to the pair of read/write bus lines 213 and 214, respectively. Therefore, an inverter formed of a PMOS transistor Q801 and an NMOS transistor Q802 and another inverter formed of a PMOS transistor Q803 and an NMOS transistor Q804 can be considered to constitute a final stage of the data amplifier 110.
A signal line 87 corresponds to the first input gate switch signal 222, and therefore, a pair of transfer gates 850 and 851 (included in the first register 830) connected to the lines 85 and 86, respectively, and controlled by the signal line 87, constitute the first input gate 113. A signal line 814 corresponds to the second input gate switch signal 233, and therefore, a pair of transfer gates 852 and 853 (included in the second register 831) connected to the lines 85 and 86, respectively, and controlled by the signal line 814, constitute the second input gate 115.
A pair of lines 812 and 813 correspond to the lines 216 and 217 in the first register 240 shown in FIG. 1, respectively, and a pair of lines 815 and 816 correspond to the lines 231 and 232 in the second register 241 shown in FIG. 1, respectively. A pair of lines 820 and 821 correspond to the pair of read bus lines 218 and 219 shown in FIG. 1, and a terminal 811 corresponds to the external input/output pin 230. In addition, a signal lines 839 corresponds to the output enable signal 224 shown in FIG. 1, and therefore, the output buffer 118 is constituted of a NAND gate 840 having two inputs connected to the lines 820 and 839, a NOR gate 841 having a first input connected to the line 821 and a second input connected through an inverter 842 to the line 839, and an inverter formed of a PMOS transistor Q805 having a gate connected to an output of the NAND gate 840 and a drain connected to the output terminal 811 and an NMOS transistor Q806 having a gate connected to an output of the NOR gate 841 and a drain connected to the output terminal 811.
A signal line 810 corresponds to the first output gate switch signal 223, and therefore, a pair of transfer gates 854 and 855 (included in the first register 830) connected to the lines 820 and 821, respectively, and controlled by the signal line 810, constitute the first output gate 114. A signal line 819 corresponds to the second output gate switch signal 234, and therefore, a pair of transfer gates 856 and 857 (included in the second register 831) connected to the lines 820 and 821, respectively, and controlled by the signal line 819, constitute the second output gate 116.
Furthermore, Reference Numerals 832, 833, 834, 835, 836 and 837 designate flipflop circuits each inserted into or connected to a corresponding line 812, 813, 815, 816, 820 and 821, for positively holding data on the corresponding line, and Reference Numerals Q81, Q82, Q83, Q84, Q85 and Q86 show reset switches associated with the flipflop circuits 832, 833, 834, 835, 836 and 837, respectively. These reset switches Q81, Q82, Q83, Q84, Q85 and Q86 are connected to receive reset control signals 88, 89, 817, 818, 817 and 818, respectively, which are activated for the purpose of resetting data on the line connected with the corresponding reset switch when the operation is changed from the reading operation to the writing operation.
As mentioned above, in the conventional synchronous DRAM, the first register 240 or 830 and the second register 241 or 831, namely, two registers are required for each one external input/output pin 230 or 811. Therefore, in the synchronous DRAM of .times.4, eight registers are required, and in the synchronous DRAM of .times.8, 16 registers are required. Furthermore, in the synchronous DRAM of .times.16, 32 registers are required, and the synchronous DRAM of .times.32, 64 registers are required.
A recent market is requiring a product having a large bit number, such as a product of .times.16 and a product of .times.32. As mentioned above with reference to FIG. 4, the register circuit itself is not so large in circuit scale, however, if 32 registers or 64 registers are required, it results in an increased chip area of the synchronous DRAM.
As a result, the conventional synchronous DRAM has the chip area larger than that of the conventional DRAM by about 10%, and the increase of the chip area also results in an increased cost. At present, since reduction of the cost will increase the demand for product, and a maker can ensure and increase profits. Therefore, a target of developers is to make the manufacturing cost as small as possible.